EDA课程设计拔河游戏机

一、总体设计思想

电子拔河游戏机是一种能容纳甲乙双方参赛游戏电路。由一排发光二极管表示拔河的“电子绳”。由甲乙双方通过按纽开关使发光二极管向一方的终点延伸，当延伸到某方的最后一个发光二极管时，则该方获胜，连续比赛多局以定胜负。

1.基本原理

本电路要求使用9个发光二极管，开机后只有中间一个发亮，此即拔河的中心点。游戏双方各持一个按钮，迅速地、不断地按动，产生脉冲，谁按得快，亮点就向谁的方向移动，每按一次，亮点移动一次。亮点移到任一方终端二极管时，这一方就获胜，此时双方按钮均无作用，输出保持，只有复位后才使亮点恢复到中心。最后用数码管显示获胜者的盘数。

由设计内容可知，首先需要一个十进制的计数器，用于对双方按钮的次数计数，并通过译码器显示在数码管上。设计要求用50MHz的频率，而设计用到的是1KHz的频率，所以要设计一个程序进行分频。其次显视控制部分设计要求在发光二极管上显示游戏状态，双方每按十次，亮点向先按十次移动一次，对脉冲进行计数，每十次移一位。需接入一个清零端，用于复位。再次运用VHDL程序语言进行各个模块的程序编写，控制电路的正常运行。最后将以上程序组装起来，就可得到所需要的拔河游戏机

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entitybaheis

port(a,b,rst,clk:instd_logic;

sg,led:outstd_logic_vector(8downto0);

bt:outstd_logic_vector(7downto0));

endbahe;

----------------------------------

architectureoneofbaheis

componentcnt10

port(clk,rst,en:std_logic;

cout:outstd_logic;

cq:outstd_logic_vector(3downto0));

endcomponent;

componentscan

port(clk:instd_logic;

a1,a2,a3,b1,b2,b3:instd_logic_vector(3downto0);

sg:outstd_logic_vector(8downto0);

bt:outstd_logic_vector(7downto0));

endcomponent;

componentlmov

port(kl,kr:instd_logic_vector(3downto0);

led:outstd_logic_vector(8downto0);

en:outstd_logic;

rst:instd_logic);

endcomponent;

signale,f,ca1,ca2,cb1,cb2:std_logic;

signalcqa1,cqa2,cqa3,cqb1,cqb2,cqb3:std_logic_vector(3downto0);

begin

u1:cnt10portmap(en=>e,rst=>rst,clk=>a,cout=>ca1,cq=>cqa1);

u2:cnt10portmap(en=>e,rst=>rst,clk=>ca1,cout=>ca2,cq=>cqa2);

u3:cnt10portmap(en=>e,rst=>rst,clk=>ca2,cq=>cqa3);

u4:cnt10portmap(en=>e,rst=>rst,clk=>b,cout=>cb1,cq=>cqb1);

u5:cnt10portmap(en=>e,rst=>rst,clk=>cb1,cout=>cb2,cq=>cqb2);

u6:cnt10portmap(en=>e,rst=>rst,clk=>cb2,cq=>cqb3);

u7:scanportmap(a1=>cqa1,a2=>cqa2,a3=>cqa3,b1=>cqb1,

b2=>cqb2,b3=>cqb3,clk=>clk,sg=>sg,bt=>bt);

u8:lmovportmap(en=>e,kl=>cqa2,kr=>cqb2,rst=>rst,led=>led);

endarchitectureone;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entitycnt10is

port(clk,rst,en:std_logic;

cout:outstd_logic;

cq:outstd_logic_vector(3downto0));

end;

architectureoneofcnt10is

begin

process(clk,rst,en)

variablecqi:std_logic_vector(3downto0);

begin

ifrst='1'then

cqi:=(others=>'0');

elsifclk'eventandclk='1'then

ifen='1'then

ifcqi<9thencqi:=cqi+1;

elsecqi:=(others=>'0');

endif;

endif;

endif;

ifcqi=9thencout<='0';

elsecout<='1';

endif;

cq<=cqi;

endprocess;

end;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entityscanis

port(clk:instd_logic;

a1,a2,a3,b1,b2,b3:instd_logic_vector(3downto0);

sg:outstd_logic_vector(8downto0);

bt:outstd_logic_vector(7downto0));

end;

architectureoneofscanis

signalcnt4:std_logic_vector(2downto0);

signala:std_logic_vector(3downto0);

signalclk1:std_logic;

begin

p1:process(cnt4)

begin

casecnt4is

when000=>bt<=10000000;a<=a1;

when001=>bt<=01000000;a<=a2;

when010=>bt<=00100000;a<=a3;

when011=>bt<=00000100;a<=b1;

when100=>bt<=00000010;a<=b2;

when101=>bt<=00000001;a<=b3;

whenothers=>bt<=00000000;

endcase;

endprocessp1;

---------------------------------

p2:process(clk)

variablect:integerrange0to50000;

begin

ifclk'eventandclk='1'then--1000HZ

ifct<49999then

ct:=ct+1;

clk1<='0';

else

ct:=0;

clk1<='1';

endif;

endif;

endprocessp2;

process(clk1)

begin

ifclk1'eventandclk1='1'then

ifcnt4<5then

cnt4<=cnt4+1;

else

cnt4<=000;

endif;

endif;

endprocess;

------------------------------------

process(a)

begin

caseais

when0000=>sg<=100000000;

when0001=>sg<=111110001;

when0010=>sg<=001001000;

when0011=>sg<=001100000;

when0100=>sg<=000110010;

when0101=>sg<=000100100;

when0110=>sg<=000000100;

when0111=>sg<=111110000;

when1000=>sg<=000000000;

when1001=>sg<=100011111;

when1010=>sg<=000100100;

when1011=>sg<=000011000;

when1100=>sg<=010001100;

when1101=>sg<=001001000;

when1110=>sg<=001000000;

when1111=>sg<=000011111;

whenothers=>null;

endcase;

endprocess;

end;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entitylmovis

port(kl,kr:instd_logic_vector(3downto0);

led:outstd_logic_vector(8downto0);

en:outstd_logic;

rst:instd_logic);

end;

architectureoneoflmovis

begin

process(rst,kl,kr)

begin

ifrst='1'thenled<=111101111;en<='1';

elsifkl-kr=1thenled<=111011111;en<='1';

elsifkl-kr=2thenled<=110111111;en<='1';

elsifkl-kr=3thenled<=101111111;en<='1';

elsifkl-kr=4thenled<=011111111;en<='0';

elsifkr-kl=1thenled<=111110111;en<='1';

elsifkr-kl=2thenled<=111111011;en<='1';

elsifkr-kl=3thenled<=111111101;en<='1';

elsifkl-kr=4thenled<=111111110;en<='0';

elsifkr-kl=0thenled<=111101111;en<='1';

elsenull;

endif;

endprocess;

end;